(1) Field of the Invention
The present invention relates to an emitter-coupled logic (ECL) gate array, and more particularly, to an ECL gate array in which each basic cell has an improved noise margin without changing a logic swing.
(2) Description of the Related Art
Various approaches have been made toward improving the performance of an ECL gate array by improving its noise margin or switching speed, but these approaches have not resolved all of the problems to be found in ECL gate arrays.
In a conventional ECL gate array, resistors for determining the logical levels, i.e., a high logic level and a low logic level of each basic cell, have fixed resistance values, which causes a problem of deteriorated noise margin in some basic cells in an ECL gate array. For example, when a basic cell is arranged too distant from a power supply pad, the power supply voltage applied to the basic cell drops because of the length of the power supply line. Therefore, both the high logic level and the low logic level of such a basic cell are lowered, and such a lowered high logic level may be errouneously detected by the next stage basic cell as a normal low logic level.
Further, when a basic cell has two output transistors connected in parallel, to shorten the rising time of the voltage at its output end, the levels of the output high and low logic levels are raised, as later described in more detail with reference to the drawings, and the thus raised low logic level may be erroneously detected by the next stage basic cell as a high logic level.
Still further, when a basic cell has two output resistors connected in parallel, to shorten the falling time of the voltage at its output end, the levels of the output high and low logic levels are lowered, as later described in more detail, and the thus lowered high logic level may be erroneously detected by the next stage basic cell as a low logic level.
Furthermore, when an ECL gate array includes a sequential circuit, the output levels of its previous stage basic cells should have a particularly improved noise margin since the internal state of a sequential circuit depends on the immediately preceding input values. Therefore, it is necessary to change the output logic levels of the above-mentioned previous stage basic cells. However, in the conventional ECL gate array, it is impossible to change the output logic levels of only the above-mentioned previous stage basic cells without changing the output logic levels of remaining basic cells.
Generally, when performing a high switching operation, the logic swing between the low logic level and the high logic level is more and more decreased, and thus the above mentioned erroneous detection becomes more serious.
In another conventional ECL gate array (as disclosed in Japanese Unexamined Patent Publication (Kokai) No. 53-60554, laid opened on May 31, 1978, filed by Inventors: Yutaka Hara et al and Applicant: Hitachi Ltd), a basic cell capable of switching between a large logic swing and a small logic swing is disclosed. However, this conventional basic cell has a disadvantage of a low switching speed due to parasitic capacitances, as later described in more detail with reference to a drawing.